Silicon-on-insulator (SOI) devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of “latchup,” which is often exhibited by complementary meta-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. sOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
SOI has been implemented in high performance CMOS integrated circuits (ICs) with a floating body node. A floating body node causes the floating body effect, which makes circuit design challenging. One example of floating body effect is the history effect that a designer needs to margin for when designing ICs. History effect means that the circuit delay is a function of the previous status of the circuit as determined by switching of the gate and drain transistor signals. Floating body effect modulates the device threshold voltage in static CMOS circuits, for example, such that a threshold voltage change causes the device drive current to vary, which in turn causes changes in circuit delay. History effect refers to this variability in delay and is determined based on input history and conditions prior to switching activity. The history effect of the delay in SOI is a design obstacle for adopting SOI technology.
Body contacts are intended to prevent the floating body effect. The floating body effect is particularly important in metal oxide semiconducting (MOS) analog technology. A node having a predetermined direct current (DC) voltage is connected to the body of a transistor when designing MOS analog circuits in order to prevent the floating body effect. The low voltage source or the high voltage source of a chip is connected to the body of a transistor depending on the type of the body in an analog circuit. Even in the case of SOI metal oxide semiconducting field effect transistors (MOSFETs) used in digital applications, bodies of transistors sometimes may have predetermined voltages applied so that the body floating effect does not occur.
Body contacts are typically positioned adjacent to SOI devices, being separated from the source and drain regions of the device by isolation regions. Therefore, body contacts are electrically connected to the SOI devices through a portion of the device having a low dopant concentration, since the higher concentration of dopants are positioned in closer proximity to the device channel by means of halo dopants and source/drain extensions. For the purposes of providing electrical connectivity of the body contact to the device, the low dopant concentration portion of the device has a higher resistance than the more highly doped portions of the device.
In order to be able to make ICs, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find a way to further downscale the dimensions of field effect transistors (FETs), such as MOSFETs and CMOS devices. Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device, while maintaining the device's electrical properties.
UTSOI devices having a thickness of about 40 nm or less are a promising option to further continue SOI CMOS device scaling. In comparison to conventional SOI devices, UTSOI devices provide a sharper sub-threshold slope (measure of the abruptness of the switching of the device), higher mobility (because the device is operated at a lower effective field) and better short channel effect control.
A disadvantage of UTSOI devices is that as the SOI film (upper Si-containing layer of SOI substrate) is thinned, the series resistance increases. The increasing series resistance of the thin SOI layer in conjunction with the low dopant concentration of the portion of the device to which body contacts typically contact SOI devices substantially reduces the effectiveness of the body contacts to eliminate the effects of floating body effects. Despite the advantages of UTSOI devices, some applications of semiconducting devices require that floating body effects be substantially eliminated.
In view of the above, there is a need for providing the performance enhancements of UTSOI for the majority of devices, while providing a means to substantially eliminate floating body effects for select devices.
Additionally, it is known within the art, that nFET devices formed atop a (110) crystal plane have decreased carrier mobility and switching speed. There is a need to provide an integrated semiconducting device in which each device is formed on a portion of a substrate having the same crystalline orientation, wherein that crystalline orientation is selected to ensure that nFET devices are not formed atop a (110) crystal plane.